100Gb/s CFP4 LR4 Receiver

Buyers for 2+ pcs,please contact me for discount.

PRODUCT FEATURES
Compliant with 100GBASE-LR4
Support line rates from 103.125 Gbps to 111.81 Gbps
Integrated LAN WDM ROSA for up to 10 km reach over S
Digital Diagnostics Monitoring Interface
Duplex LC optical receptacle
No external reference clock
Single 3.3 V power supply
Case operating temperature range:0°C to 70°C

Power dissipation < 2W

APPLICATIONS
Local Area Network (LAN)
Data Center
Ethernet switches and router applications

STANDARD
Compliant to IEEE 802.3ba
Compliant to CFP MSA CFP4 Hardware Specification
Compliant to CFP MSA Management Interface Specification

Outline Dimensions

General Description
OPMEDIA 100G CFP4 LR4 optical Receiver integrates receiver on one module. In the receive side, the
four lanes of optical data streams are optically de-multiplexed by the integrated optical de-multiplexer.
Each data stream is recovered by a PIN photo-detector and trans-impedance amplifier, retimed. This
module features a hot-pluggable electrical interface, low power consumption and MDIO management
interface.

The module provides an aggregated signaling rate from 103.125 Gbps to 111.81 Gbps. It is compliant
with IEEE 802.3 ba 100GBASE-LR4 and ITU-T G.959.1, and OIF CEI-28G-VSR. The MDIO
management interface complies with IEEE 802.3 Clause 45 standard. The transceiver complies with CFP
MSA CFP4 Hardware Specification, CFP MSA Management Interface Specification, and OIF
CEI-28G-VSR standards.
Receiver
The receiver takes incoming combined four lanes optical data from line rate of 25.78 Gbps to 27.95 Gbps

through an industry standard LC optical connector. The four incoming wavelengths are separated by an
optical de-multiplexer into four separated channels. Each output is coupled to a PIN photo-detector. The
electrical currents from each PIN photo-detector are converted to a voltage with a high-gain
trans-impedance amplifier. The electrical output is recovered and retimed by the CDR chip. The four
lanes of reshaped electrical signals are output to RDxp and RDxn pins.
Low Speed Signaling
Low speed signaling is based on low voltage CMOS (LVCMOS) operating at a nominal voltage of 3.3 V
for the control and alarm signals, and at a nominal voltage of 1.2 V for MDIO address, clock and data
signals. All low speed inputs and outputs are based on the CFP MSA CFP4 Hardware Specification and
CFP MSA Management Interface Specification.
MDC/MDIO: Management interface clock and data lines.
GLB-ALEMn: Output pin. When asserted low indicates that the module has detected an alarm condition
in any MDIO alarm register.
TX-Disable: Input pin. When asserted high or left open the transmitter output is turned off. When

Tx-Dsiable is asserted low or grounded the module transmitter is operating normally. Pulled up with 4.7

k ohm to 10 k ohm resistors to 3.3 V inside the CFP4 module.
MOD-LOPWR: Input pin. When asserted high or left open the CFP4 module is in low power mode.
When asserted low or grounded the module is operating normally. Pulled up with 4.7 k ohm to 10 k ohm
resistors to 3.3 V inside the CFP4 module.
MOD-RSTn: Input pin. When asserted low or grounded the module is in Reset mode. When asserted
high or left open the CFP4 module is operating normally after an initialization process. Pulled down with
4.7 k ohm to 10 k ohm resistors to ground inside the CFP4 module.
Mod_ABS: Output pin. Asserted high when the CFP4 module is absent and is pulled low when the CFP4
module is inserted.
RX-LOS: Output pin. Asserted high when insufficient optical power for reliable signal reception is
received.